R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 252

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 215 of 802
15.3.9
Table 15.9
Notes:
Table 15.10
Operation
Data read
Data write
Vector Read
1. For the number of clock cycles required for data read/write, see Table 15.10 Number of Clock
2. For the number of clock cycles required for control data write-back, see Table 15.8 Specifications
Table 15.9 shows the Operations Following DTC Activation and Required Number of Cycles for each
operation.
Table 15.10 shows the Number of Clock Cycles Required for Data Transfers.
Data is transferred as described below, when the DTBLSj (j = 0 to 23) register = N,
(1) When N = 2n (even), two-byte transfers are performed n times.
(2) When N = 2n + 1 (odd), 2-byte transfers are performed n times followed by one 1-byte transfer.
From Tables 15.9 and 15.10, the total number of required execution cycles can be obtained by the following
formula:
Number of required execution cycles = 1 + [formula A] + 2
transfer times for which CHNE is set to 1] + 1)
(1) For N = 2n (even)
(2) For N = 2n+1 (odd)
To read data from or write data to the register that to be accessed in 16-bit units, set an even value of 2 or greater
to the DTBLSj (j = 0 to 23) register.
The DTC performs accesses in 16-bit units.
Cycles Required for Data Transfers .
of Control Data Write-Back Operation .
: Sum of the cycles for the number of transfer times performed by one activation source ([the number of
1
Formula A = J + n • SK2 + n • SL2
Formula A = J + n • SK2 + 1 • SK1 + n • SL2 + 1 • SL1
J: Number of cycles required to read control data (5 cycles) + number of cycles required to write back control data
Number of DTC Execution Cycles
1-byte SK1
2-byte SK2
1-byte SL1
2-byte SL2
Transfers
Unit of
Operations Following DTC Activation and Required Number of Cycles
Number of Clock Cycles Required for Data Transfers
(During DTC Transfers) Internal ROM
Address
Even
Read
Internal RAM
1
1
5
Control Data Read
Oct 30, 2009
1
1
Address
Odd
2
2
Write-back
(Program ROM)
(Note 2)
—
—
1
2
(Data flash)
Internal
ROM
—
—
2
4
Data Read
(Note 1)
Address
Even
(Word Access)
2
2
SFR
2
2
Address
Odd
Data Write
4
4
(Note 1)
Access)
(Byte
SFR
2
4
2
4
Internal Operation
(DTC control data area)
Address
Even
1
1
SFR
1
1
1
Address
Odd
15. DTC
2
2