R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 658

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 621 of 802
Figure 28.5
28.4.2
LINCR register
TRAIC register
LINST register
LINST register
RXDSF flag in
SBDCT flag in
SFDCT flag in
Figure 28.5 shows an Operating Example during Header Field Reception in slave mode. Figures 28.6 through
28.8 show examples of Header Field Reception Flowchart.
During header field reception, the hardware LIN operates as follows:
(1) When 1 is written to the LSTART bit in the LINCR register for the hardware LIN, Synch Break detection is
(2) When a low-level signal is input for a duration equal to or longer than the period set in timer RA, the
(3) The hardware LINA receives a Synch Field (55h) and measures the period of the start bit and bits 0 to 6 is
(4) When the Synch Field measurement is completed, the SFDCT flag in the LINST register is set to 1. If the
(5) After the Synch Field measurement is completed, a transfer rate is calculated from the timer RA count
(6) After the hardware LIN completes receiving the ID field, it performs communication for a response field.
RXD0 input
for UART0
RXD0 pin
enabled.
hardware LIN detected it as a Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated. Then the hardware LIN
transits to the Synch Field measurement.
using timer RA. At this time, whether to input the Synch Field signal to RXD0 of UART0 can be selected
by the SBE bit in the LINCR register.
SFIE bit in the LINCR register is set to 1, a timer RA interrupt is generated.
value. The rate is set in UART0 and registers TRAPRE and TRA for timer RA are set again. Then the
hardware LIN receives an ID field via UART0.
IR bit in
Slave Mode
Operating Example during Header Field Reception
1
0
1
0
1
0
1
0
1
0
1
0
The above applies under the above conditions:
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
(1)
Oct 30, 2009
1 is written to the LSTART bit
in the LINCR register.
Synch Break
(2)
(3)
This period is measured.
Set to 0 when an interrupt request is acknowledged
or by a program.
1 is written to the B1CLR bit
in the LINST register.
Synch Field
(4)
(5)
1 is written to the B0CLR bit
in the LINST register.
The flag is set to 0 after Synch Field
measurement is completed.
IDENTIFIER
28. Hardware LIN
(6)