R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 194

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 157 of 802
Figure 11.3
11.3.4
Address Bus
CPU Clock
Data Bus
The following describes an interrupt sequence which is performed from when an interrupt request is
acknowledged until the interrupt routine is executed.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instruction, if an interrupt request is generated while the
instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt
sequence is performed as indicated below.
Figure 11.3 shows the Time Required for Executing Interrupt Sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address
(2) The FLG register is saved to a temporary register
(3) The I, D and U flags in the FLG register are set as follows:
(4) The CPU internal temporary register
(5) The PC is saved on the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt
routine.
Notes:
Note:
WR
RD
1. The indeterminate state depends on the instruction queue buffer.
00000h. The IR bit for the corresponding interrupt is set to 0 (no interrupt requested).
sequence.
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is
executed.
A read cycle occurs when the instruction queue buffer is ready to accept instructions.
1. These registers cannot be accessed by the user.
2. Refer to 11.7 Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication
Interrupt Sequence
Unit, I
for the IR bit operations of the above interrupts.
1
Time Required for Executing Interrupt Sequence
2
Address
0000h
2
information
C bus Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources)
Interrupt
3
4
Oct 30, 2009
5
Undefined
Undefined
Undefined
6
7
(1)
is saved on the stack.
8
SP-2 SP-1
9
content
SP-2
10
(1)
content
SP-1
in the CPU immediately before entering the interrupt
SP-4
11
content
SP-4
12
SP-3
content
SP-3
13
VEC
14
content
VEC
15
VEC+1
VEC+1
content
16
17
(2)
VEC+2
VEC+2
content
18
11. Interrupts
19
PC
20