R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 609

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 572 of 802
26.5.2
Figure 26.11 shows an Example of Synchronous Serial Communication Unit Operation during Data
Transmission (4-Wire Bus Communication Mode, 8-Bit SSU Data Transfer Length). During the data transmit
operation, the synchronous serial communication unit operates as described below (the data transfer length can
be set from 8 to 16 bits using the SSBR register).
When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a
slave device, it outputs data in synchronization with the input clock while the SCS pin is low-input state.
When the transmit data is written to the SSTDR register after setting the TE bit to 1 (transmission enabled), the
TDRE bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is
transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data transferred from registers
SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1 at this time, the TXI
interrupt request is generated.
After one frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers
SSTDR to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while TDRE is set
to 1, TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is
set to 1) and the state is retained. When the TEIE bit in the SSER register is set to 1 (transmit-end interrupt
request enabled) at this time, the TEI interrupt request is generated. The SSCK pin remains high after transmit-
end and the SCS pin is held high. When transmitting continuously while the SCS pin is held low, write the next
transmit data to the SSTDR register before transmitting the 8th bit.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while
the SCS pin is placed in high-impedance state when operating as the master device. The SSI pin is placed in
high-impedance state while the SCS pin is high-input state when operating as a slave device.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 26.6
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)).
Data Transmission
Oct 30, 2009
26. Synchronous Serial Communication Unit (SSU)