R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 562

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 525 of 802
Figure 24.10
Figure 24.11
24.4.4
24.4.5
The data written to the U2TB register has its logic inverted before being transmitted. Similarly, the received
data has its logic inverted when read from the U2RB register. Figure 24.10 shows the Serial Data Logic
Switching.
This function inverts the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all I/O data
(including bits for start, stop, and parity) are inverted. Figure 24.11 shows the TXD and RXD I/O Inversion.
Transfer clock
TXD2
(not inverted)
Transfer clock
TXD2
(inverted)
(1) U2LCH bit in U2C1 Register = 0 (not inverted)
(2) U2LCH Bit in U2C1 Register = 1 (inverted)
The above applies under the following conditions:
Serial Data Logic Switching Function
TXD and RXD I/O Polarity Inverse Function
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge of the transfer clock)
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
Transfer clock
TXD2
(not inverted)
RXD2
(not inverted)
Transfer clock
TXD2
(inverted)
RXD2
(inverted)
(1) IOPOL Bit in U2MR Register = 0 (not inverted)
(2) IOPOL Bit in U2MR Register = 1 (inverted)
The above applies under the following conditions:
TXD and RXD I/O Inversion
Serial Data Logic Switching
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
“H”
“H”
“H”
“H”
“L”
“L”
“L”
“L”
“H”
“H”
“H”
“H”
“H”
“H”
“L”
“L”
“L”
“L”
“L”
“L”
Oct 30, 2009
ST
ST
ST
ST
ST
D0
D0
ST
D0
D0
D0
D0
D1
D1
D1
D1
D1
D2
D2
D1
D2
D2
D2
D3
D3
D2
D3
D3
D3
D4
D4
D3
D4
D4
D4
D5
D4
D5
D5
D5
D5
D6
D6
D5
D6
D6
D7
D7
D6
D6
ST: Start bit
P: Parity bit
SP: Stop bit
D7
D7
D7
D7
P
P
SP
SP
P
P
P
P
24. Serial Interface (UART2)
ST: Start bit
P: Parity bit
SP: Stop bit
SP
SP
SP
SP