R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 505

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 468 of 802
Figure 22.13
22.6.1
22.6.2
Table 22.10
Compare match with TRGGRA register
Compare match with TRGGRB register
Figure 22.13 shows a Procedure Example for Setting PWM Mode.
Figure 22.14 shows an Operating Example in PWM Mode (1).
When PWM mode is selected while the TRGIOASEL0 bit in the TRGSR register is set to 1, the TRGIOA pin
automatically functions as an output pin, high-level output at compare match with the TRGGRA register is
selected, and low-level output at compare match with the TRGGRB register is selected. However, regardless of
the setting of the TRGIOR register, the TRGIOB pin functions as an I/O port.
This example applies when a compare match with the TRGGRA or TRGGRB register is set as the counter clear
source for the TRG register. The initial status of the TRGIOA pin depends only on the counter clear sources.
This correspondence is shown in Table 22.10.
Counter Clear Source
Select the counter clock
Select the counter clear
Procedure Example for Setting PWM Mode
Operating Example
Count operation starts
Set PWM mode
Set TRGGRA
Set TRGGRB
Procedure Example for Setting PWM Mode
Correspondence between Initial Status of TRGIOA Pin and Counter Clear Sources
PWM mode
PWM mode
source
Oct 30, 2009
(1)
(2)
(3)
(4)
(5)
(6)
(1) Use bits TCK0 to TCK2 in the TRGCR register to select
(2) Use bits CCLR0 and CCLR1 in the TRGCR register to select
(3) Set the high-level output timing for PWM output waveforms in
(4) Set the low-level output timing for PWM output waveforms in
(5) Use the PWM bit in the TRGMR register to select PWM mode.
(6) Set the TSTART bit in the TRGMR register to 1 to start the count
the count source. When an external clock is selected,
use bits CKEG0 and CKEG1 in the TRGCR register to select
the edge of the external clock.
the counter clear source.
the TRGGRA register.
the TRGGRB register.
When PWM mode is selected, TRGGRA and TRGGRB are
set as the output compare registers for setting the high-level output
or low-level output timing for PWM output waveforms, regardless of
the content of the TRGIOR register.
While the TRGIOASEL0 bit in the TRGSR register is set to 1, the
TRGIOA pin automatically functions as a PWM output pin.
However, regardless of the setting of the TRGIOR register, the
TRGIOB pin functions as an I/O port.
operation of the TRG register.
Initial Status of TRGIOA Pin
High
Low
22. Timer RG