R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 368

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 331 of 802
Figure 20.9
TRDIOji input signal
20.3.18 Digital Filter
TRDCLK
Sampling clock
TRDIOji input signal
Input signal through
digital filtering
The TRDIOji input is sampled and the level is determined when the sampled input level matches three times.
The digital filter function and sampling clock can be selected using the TRDDFi register.
Figure 20.9 shows a Block Diagram of Digital Filter.
fC2
f32
f8
f4
f2
f1
ITCLKi = 1
ITCLKi = 0
Timer RD operation clock
= 011b
i = 0 or 1, j = either A, B, C, or D
ITCLK0, ITCLK1: Bits in TRDECR register
TCK0 to TCK2: Bits in TRDCRi register
DFCK0 to DFCK1 and DFj: Bits in TRDDF register
IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register
IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register
= 100b
Block Diagram of Digital Filter
= 010b
Clock period selected by
bits TCK2 to TCK0 or
bits DFCK1 to DFCK0
= 101b
D
D
= 001b
= 000b
Latch
Latch
C
f1
C
Q
Q
Count source
D
Oct 30, 2009
f32
f8
f1
Latch
C
= 01b
= 10b
= 00b
= 11b
DFCK1 to DFCK0
Q
Transmission cannot be
performed without 3-time match
because the input signal is
assumed to be noise.
D
Latch
C
Sampling clock
Q
D
Latch
C
Q
detection
Match
circuit
Signal transmission delayed
up to 5-sampling clock
Recognition of the
signal change with
3-time match
1
0
DFj
Edge detection
IOA2 to IOA0
IOB2 to IOB0
IOC3 to IOC0
IOD3 to IOD0
circuit
20. Timer RD