R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 341

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 304 of 802
Figure 19.18
TRCGRB register
TRCGRD register
TRCCR2 register
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
TRCTRG input
TSTART bit in
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is low, high-level output at compare match with the TRCGRC register,
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).
CSEL bit in
IMFC bit in
IMFA bit in
IMFB bit in
low-level output at compare match with the TRCGRB register).
Count source
FFFFh
TRC register value
0000h
m
1
0
1
0
1
0
1
0
1
0
n
p
Operating Example in PWM2 Mode (TRCTRG Trigger Input Enabled)
“L” initial output
n
“H” output at
TRCGRC register
compare match
Transfer from buffer register to general register
n+1
p+1
Count starts
when TSTART
bit is set to 1.
Oct 30, 2009
Transfer
“L” output at
TRCGRB register
compare match
n
Set to 0 by
a program.
n
Inactive level so
TRCTRG input is
enabled.
Previous value
when TSTART
bit is set to 0.
p+1
TRC register (counter) is cleared
by TRCTRG pin trigger input.
is retained
Change by a program.
Transfer
Return to initial value
when TSTART bit is set to
0.
n
Set to 0 by
a program.
Set to 1 by
a program.
Set to 0000h
by a program.
Transfer from buffer register to general register
m+1
n+1
p+1
Transfer
Active level so TRCTRG
input is disabled.
m: Value set in TRCGRA register
n: Value set in TRCGRB register
p: Value set in TRCGRC register
Count starts at
TRCTRG pin
trigger input.
n
Set to 0 by
a program.
Next data
TRC register is cleared
by TRCGRA register
compare match.
Set to 0 by
a program.
19. Timer RC
Count stops
because
CSEL bit is
set to 1.
TSTART bit
is set to 0.
Transfer