R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 513

MCU FLASH 96+4KB 100LQFP

R5F2L3AAANFP#U1

Manufacturer Part Number
R5F2L3AAANFP#U1
Description
MCU FLASH 96+4KB 100LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet

Specifications of R5F2L3AAANFP#U1

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F2L3AAANFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 476 of 802
22.9
Figure 22.22
22.9.1
22.9.2
The phase difference and overlap between the external input signals from pins TRGCLKA and TRGCLKB
should be 1.5 f1 or more, respectively. The pulse width should be 2.5 f1 or more. Figure 22.22 shows the Phase
Difference, Overlap, and Pulse Width in Phase Counting Mode.
When writing to the TRG register or TRGCR register, make sure the TSTART bit in the TRGMR register to 0
(count stops).
TRGCLKA input
TRGCLKB input
Notes on Timer RG
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Timer RG Counter (TRG)
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Phase difference
Oct 30, 2009
Overlap
Phase difference
Overlap
Pulse width
Phase difference and overlap: 1.5 f1 or more
Pulse width: 2.5 f1 or more
Pulse width
22. Timer RG

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