R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 395

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 358 of 802
20.5.6
20.5.7
Notes:
1. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0139h
Address 013Ah
stops).
is enabled.
Symbol
Symbol
PWMC0 PWM mode of TRDIOC0 select bit
PWMD0 PWM mode of TRDIOD0 select bit
PWMC1 PWM mode of TRDIOC1 select bit
PWMD1 PWM mode of TRDIOD1 select bit
PWMB0 PWM mode of TRDIOB0 select bit
PWMB1 PWM mode of TRDIOB1 select bit
Symbol
ADTRG
Symbol
STCLK
Bit
Bit
PWM3
CMD0
CMD1
ADEG
OLS0
OLS1
Timer RD PWM Mode Register (TRDPMR) in PWM Mode
Timer RD Function Control Register (TRDFCR) in PWM Mode
—
—
PWM3
b7
b7
—
1
1
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Combination mode select bit
Normal-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
Counter-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
A/D trigger enable bit
(in complementary PWM mode)
A/D trigger edge select bit
(in complementary PWM mode)
External clock input select bit
PWM3 mode select bit
PWMD1 PWMC1 PWMB1
STCLK
b6
b6
0
0
Oct 30, 2009
Bit Name
Bit Name
ADEG
b5
b5
0
0
(2)
ADTRG
(1)
b4
b4
0
0
0: Timer mode
1: PWM mode
0: Timer mode
1: PWM mode
OLS1
b3
b3
—
1
0
Set to 00b (timer mode, PWM mode, or PWM3
mode) in PWM mode.
Disabled in PWM mode.
0: External clock input disabled
1: External clock input enabled
Set to 1 (other than PWM3 mode) in PWM
mode.
PWMD0 PWMC0 PWMB0
OLS0
b2
b2
0
0
Function
CMD1
Function
b1
b1
0
0
CMD0
b0
b0
0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—