R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 704

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 667 of 802
32.2.3
32.2.4
Bit
b0
b1
b2
b3
b4
b5
b6
b7
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0202h
Address 0203h
Symbol
Symbol
LDFR20 LCD data display
LDFR21
Symbol
LDSPC LCD data display
LRVRS LCD display
LDFR0
LDFR1
LDFR2
Symbol
LPSC0
LPSC1
LPSC2
LCKS0
LCKS1
Bit
Bit
—
LCD Display Control Register (LCR2)
LCD Clock Control Register (LCR3)
—
—
—
LCKS1
LCD data display
control interval
select bit 1
(synchronized
with the frame
frequency)
control enable bit
control mode
select bit
control interval
select bit 2
(synchronized
with timer RE)
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
b7
b7
—
X
0
Division ratio select bit
Reserved bits
LCD clock source select bit
Bit Name
LDFR21 LDFR20
LCKS0
b6
b6
0
0
Oct 30, 2009
Bit Name
b2 b1 b0
0: Data display control disabled
1: Data display control enabled
0: Blink display
1: Invert display
b6 b5
0 0 0: Display control interval = f(FR)
0 0 1: Display control interval = f(FR)
0 1 0: Display control interval = f(FR)
0 1 1: Display control interval = f(FR)
1 0 0: Display control interval = f(FR)
1 0 1: Do not set.
1 1 0: Do not set.
1 1 1: Display control interval =
0 0 : Settings of bits LDER0 to LDER2 enabled
0 1 : 0.25-second interval
1 0 : 0.5-second interval
1 1 : 1-second interval
b5
b5
—
0
0
LRVRS
b4
b4
—
0
0
b2 b1 b0
Set to 0.
b7 b6
0 0 0: No division
0 0 1: Divide-by-2
0 1 0: Divide-by-4
0 1 1: Divide-by-8
1 0 0: Divide-by-16
1 0 1: Divide-by-32
1 1 0: Divide-by-64
1 1 1: Do not set.
0 0: f32
0 1: fC-LCD
1 0: Do not set.
1 1: Do not set.
LDSPC
b3
b3
—
0
0
LDFR2
LPSC2
Function
b2
b2
0
0
(other than 1/3 duty)
× 16 counts
× 32 counts
× 64 counts
× 128 counts
× 256 counts
Static
Other than LDTY2
to LDTY0 = 010b
Function
LDFR1
LPSC1
b1
b1
0
0
32. LCD Drive Control Circuit
LDFR0
LPSC0
b0
b0
0
0
× 12 counts
× 24 counts
× 48 counts
× 96 counts
× 192 counts
Static
LDTY2 to LDTY0
(1/3 duty)
= 010b
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—