R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 532

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 495 of 802
Figure 23.7
• Receive Timing Example When Transfer Data is 8 Bits Long (Parity Disabled, One Stop Bit)
UiBRG output
Transfer clock
UiC1 register
SiRIC register
UiC1 register
RE bit in
RI bit in
IR bit in
RXDi
The above applies under the following conditions:
Receive Timing in UART Mode
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 0 (one stop bit)
i = 0 or 1
1
0
1
0
1
0
Reception starts when a transfer clock is
generated at the falling edge of the start bit.
Oct 30, 2009
Start bit
“L” is determined.
D0
Received data capture
Set to 0 when an interrupt request is acknowledged or by a program.
D1
Data transfer from UARTi receive register to
UiRB register
23. Serial Interface (UARTi (i = 0 or 1))
D7
Stop bit