R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 764

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 727 of 802
Table 33.11
FMR21, FMR22: Bits in FMR2 register
Note:
EW1
Mode
1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0.
Data flash During auto-erasure
Program
ROM
Erase/
Target
Write
CPU Rewrite Mode Interrupts (3)
(suspend enabled)
During auto-erasure
(suspend disabled
During
auto-programming
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
During
auto-programming
or FMR22 = 0)
or FMR22 = 0)
Status
Oct 30, 2009
• Watchdog Timer
• Oscillation Stop Detection
• NMI
When an interrupt request is acknowledged,
interrupt handling is executed.
If the FMR22 bit is set to 1, the FMR21 bit is
automatically set to 1. The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit
is set to 0, set the FMR 21 bit to 1 during
interrupt handling. The flash memory suspends
auto-programming after td(SR-SUS).
While auto-erasure is being suspended, any
block other than the block during auto-erasure
execution can be read. Auto-erasure can be
restarted by setting the FMR21 bit is set to 0.
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
When an interrupt request is acknowledged,
auto-erasure or auto-programming is forcibly
stopped immediately and the flash memory is
reset. Interrupt handling starts when the flash
memory restarts after the fixed period.
Since the block during auto-erasure or the
address during auto-programming is forcibly
stopped, the normal value may not be read. After
the flash memory restarts, execute auto-erasure
again and ensure it completes normally.
The watchdog timer does not stop during the
command operation, so interrupt requests may
be generated. Initialize the watchdog timer
regularly using the erase-suspend function.
(Note 1)
• Undefined Instruction
• INTO Instruction
• BRK Instruction
• Single Step
• Address Match
• Address Break
When an interrupt request is
acknowledged, interrupt handling
is executed.
If erase-suspend is required, set
the FMR 21 bit to 1 during
interrupt handling. The flash
memory suspends auto-erasure
after td(SR-SUS).
While auto-erasure is being
suspended, any block other than
the block during auto-erasure
execution can be read. Auto-
erasure can be restarted by
setting the FMR21 bit in the FMR2
register is set to 0 (erase restart).
Not usable during auto-erasure or
auto-programming.
33. Flash Memory
(Note 1)