R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 250

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 213 of 802
Figure 15.10
15.3.6
15.3.7
When the CHNE bit in the DTCCRj (j = 0 to 22) register is 1 (chain transfers enabled), multiple data transfers
can be continuously performed by one activation source. Figure 15.10 shows a Flow of Chain Transfers.
When the DTC is activated, one control data is selected according to the data read from the DTC vector address
corresponding to the activation source, and the selected control data is read from the DTC control data area.
When the CHNE bit for the control data is 1 (chain transfers enabled), the next control data immediately
following the current control data is read and transferred after the current transfer is completed. This operation
is repeated until the data transfer with the control data for which the CHNE bit is 0 (chain transfers disabled) is
completed.
Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed in normal
mode, and when the data transfer causing the DTCCTj register value to change to 0 is performed while the
RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode, the interrupt request
corresponding to the activation source is generated for the CPU during DTC operation. However, no interrupt
request is generated for the CPU when the activation source is SSU/I
status.
Interrupt requests for the CPU are affected by the I flag or interrupt control register. In chain transfers, whether
the interrupt request is generated or not is determined either by the number of transfer times specified for the
first type of the transfer or the RPTINT bit. When an interrupt request is generated for the CPU, the bit among
bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 6) registers corresponding to the activation source are set
to 0 (activation disabled).
Chain Transfers
Interrupt Sources
Flow of Chain Transfers
CHNE: Bit in DTCCRj register
DTC control data area
Control data 1
Control data 2
Oct 30, 2009
CHNE = 1
CHNE = 0
Write back control data 1
Write back control data 2
DTC activation source
End of DTC transfers
Read control data 1
Read control data 2
Read DTC vector
Transfer data
Data transfer
generation
2
C bus transmit data empty or flash ready
15. DTC