R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 458

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 421 of 802
20.10 Notes on Timer RD
20.10.1 TRDSTR Register
Table 20.18
20.10.2 TRDi Register (i = 0 or 1)
20.10.3 TRDSRi Register (i = 0 or 1)
When the CSELi bit is set to 1, write 0 to the TSTARTi bit and the
count stops.
When the CSELi bit is set to 0, the count stops at compare match
between registers TRDi and TRDGRAi.
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•
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When writing the value to the TRDSRi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Set the TRDSTR register using the MOV instruction.
When the CSELi (i = 0 or 1) is set to 0 (count stops at compare match between registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
When the CSELi bit is set to 0, write 0 to the TSTARTi bit to change other bits without changing the
TSTARTi bit.
To stop counting by a program, write 0 to the TSTARTi bit after setting the CSELi bit to 1. If 1 is written to
the CSELi bit and 0 is written to the TSTARTi bit is set to 0 at the same time (with one instruction), the count
cannot be stopped.
Table 20.18 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops while the TRDIOji (j =
A, B, C, or D) pin is used for the timer RD output.
When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register is
set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then
write.
If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to the TRDi
register, the value is not written and the TRDi register is set to 0000h.
These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi register.
- 001b (Clear by the TRDi register at compare match with the TRDGRAi register.)
- 010b (Clear by the TRDi register at compare match with the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear by the TRDi register at compare match with the TRDGRCi register.)
- 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example
Program example
TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
Stopping Count
Oct 30, 2009
L1:
L1:
MOV.W
JMP.B
MOV.W
MOV.B
JMP.B
MOV.B
#XXXXh, TRD0
L1
TRD0,DATA
#XXh, TRDSR0
L1
TRDSR0,DATA
Holds the output level immediately before
the count stops.
Holds the output level after the output
changes by the compare match.
TRDIOji Pin Output when Count Stops
;Write
;JMP.B
;Read
;Write
;JMP.B
;Read
20. Timer RD