R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 351

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 314 of 802
20.2.4
In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode, and
PWM3 mode, the TRDIOji (i = 0 or 1, j = either A, B, C, or D) output pin can be forcibly set to a programmable
I/O port by the INT0 pin input, and pulse output can be cut off.
The pins used for output in the above function or modes can function as the output pin of timer RD when the
applicable bit in the TRDOER1 register is set to 0 (timer RD output enabled). When the PTO bit in the
TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled), all bits in the TRDOER1
register are set to 1 (timer RD output disabled, TRDIOji output pin functions as a programmable I/O port) after
a low-level signal is applied to the INT0 pin. The TRDIOji output pin is set to a programmable I/O port after a
low-level signal is applied to the INT0 pin and waiting for one or two cycles of the timer RD operating clock
(refer to Table 20.1 Timer RD Operating Clocks).
Set the following to use this function:
• Set the pin status (high impedance, low-level, or high-level output) to pulse output forced cutoff by registers
• Set the INT0EN bit in the INTEN register to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge).
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Set the INT0 digital filter by bits INT0F0 and INT0F1 in the INTF register.
• Set the PTO bit in the TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled).
According to the selection of the POL bit in the INT0IC register and change of the INT0 pin input, the IR bit in
the INT0IC register is set to 1 (interrupt requested). Refer to 11. Interrupts for details of interrupts.
P2 and PD2.
Pulse Output Forced Cutoff
Oct 30, 2009
20. Timer RD