R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 556

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 519 of 802
24.4
Table 24.5
Notes:
Transfer data format
Transfer clock
Transmission/reception control Selectable from the CTS function, RTS function, or CTS/RTS function disabled.
Transmit start conditions
Receive start conditions
Interrupt request generation
timing
Error detection
Selectable functions
In UART mode, data is transmitted and received after setting the desired transfer rate and transfer data format.
Table 24.5 lists the UART Mode Specifications. Table 24.6 lists the Registers Used and Settings in UART Mode.
1. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC
2. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
register remains unchanged.
from the UART2 receive register to the U2RB register.
Clock Asynchronous Serial I/O (UART) Mode
Item
UART Mode Specifications
Oct 30, 2009
• Character bits (transfer data): Selectable from 7, 8, or 9 bits
• Start bit:1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bits: Selectable from 1 bit or 2 bits
• The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(16(n + 1))
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1))
To start transmission, the following requirements must be met:
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data in the U2TB register).
• If the CTS function is selected, input to the CTS2 pin is low.
To start reception, the following requirements must be met:
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• Start bit detection
For transmission, one of the following conditions can be selected.
• The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
• The U2IRS bit is set to 1 (transmission completed):
For reception
• When data is transferred from the UART2 receive register to the U2RB register
• Overrun error
• Framing error
• Parity error
• Error sum flag
• LSB first, MSB first selection
• Serial data logic switching
• TXD, RXD I/O polarity switching
• RAD2 digital filter selection
fEXT: Input from CLK2 pin n: Value set in U2BRG register: 00h to FFh
When data is transferred from the U2TB register to the UART2 transmit register
(at start of transmission).
When data transmission from the UART2 transmit register is completed.
(at completion of reception).
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the bit one before the last stop bit of the
next unit of data.
This error occurs when the set number of stop bits is not detected.
This error occurs when if parity is enabled, the number of 1’s in the parity and
character bits does not match the set number of 1’s.
This flag is set to 1 if an overrun, framing, or parity error occurs.
Whether data transmission/reception begins with bit 0 or begins with bit 7 can be
selected.
This function inverts the logic of transmit/receive data. Start and stop bits are not
inverted.
This function inverts the polarities of the TXD pin output and RXD pin input. The
logic levels of all I/O data are inverted.
The digital filter for the RXD2 input signal can be enabled or disabled.
fj = f1, f8, f32, fC n = Value set in U2BRG register: 00h to FFh
(2)
(1)
(2)
Specification
24. Serial Interface (UART2)