R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 713

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 676 of 802
Figure 32.5
32.4.5
32.4.6
Table 32.5
SEG0 to SEG55
COM0 to COM7
CL1 and CL2
VL1
VL2 to VL4
The bias is selected by setting bits LBAS0 and LBAS1, and the duty is selected by setting bits LDTY0 to
LDTY2. Either a segment panel control waveform or a dot matrix panel control waveform is selected by setting
the LWAV bit. An LCD display is enabled by setting the LDSPE bit to 1, and the display is started by setting
LSTAT bit to 1.
The LCD display contents are changed by rewriting the contents of the LCD display data register and the LCR2
register.
The status of the LCD display function pins selected by bits LSE00 to LSE60 in registers LSE0 to LSE7 are
shown below. LCD control is restarted by means of the same operation as that used to make LCR0 register
settings, as shown the LCD drive control procedure in Table 34.4.
Pin Name
LCD Data Display
Pin Status in Stop Mode
Pin Connection and Voltage Levels when Voltage Multiplier is Used
LCD Display Function Pin Status in Stop Mode
(Note 1)
Outputs a low-level signal.
Outputs a low-level signal.
Outputs a low-level signal.
• When external division resistors are used (the voltage multiplier is disabled by setting the
• When the voltage multiplier is used with the VL1 externally-input voltage (the LVUPE bit is
• When the voltage multiplier is used with the VL1 internally-generated voltage (the LVUPE
High-impedance state
Note:
1/4 bias selected
1/2 bias selected
LVUPE bit in the LCR1 register to 0)
High-impedance state.
set to 1 and the LVURS bit is set to 0)
High-impedance state.
bit is set to 1 and the LVURS bit is set to 1)
Outputs the internally-generated voltage.
CL2
CL1
VL4
VL3
VL2
VL1
1. When VL1 is generated internally (LVURS = 1).
Oct 30, 2009
When LVURS is 0, supply VL1 externally.
4VL1
3VL1
2VL1
CL
C4
C3
C2
C1
(Note 1)
Pin Status
1/3 bias selected
CL2
CL1
VL4
VL3
VL2
VL1
3VL1
2VL1
CL
C4
C2
C1
32. LCD Drive Control Circuit