R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 598

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 561 of 802
26.3.3
Table 26.3
CEIE, RIE, TEIE, TIE: Bits in SSER register
ORER, RDRF, TEND, TDRE: Bits in SSSR register
Transmit data empty
Transmit end
Receive data full
Overrun error
Conflict error
If the generation conditions in Table 26.3 are met, an interrupt request of the synchronous serial communication
unit is generated. Set each interrupt source to 0 by the synchronous serial communication unit interrupt routine.
However, bits TDRE and TEND are automatically set to 0 by writing transmit data to the SSTDR register and the
RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data
transferred from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register. If
the TDRE bit is further set to 0 (data not transferred from registers SSTDR to SSTRSR), additional 1 byte may be
transmitted.
The synchronous serial communication unit has five interrupt requests: transmit data empty, transmit end,
receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the synchronous
serial communication unit interrupt vector table, determining interrupt sources by flags is required.
Table 26.3 shows the Interrupt Requests of Synchronous Serial Communication Unit.
Interrupt Request
Interrupt Requests
Interrupt Requests of Synchronous Serial Communication Unit
Oct 30, 2009
TXI
TEI
RXI
OEI
CEI
Abbreviation
26. Synchronous Serial Communication Unit (SSU)
TIE = 1 and TDRE = 1
TEIE = 1 and TEND = 1
RIE = 1 and RDRF = 1
RIE = 1 and ORER = 1
CEIE = 1 and CE = 1
Generation Condition