R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 143

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 106 of 802
7.
The bus cycles differ when accessing ROM/RAM and when accessing SFR.
Table 7.1 lists the Bus Cycles by Access Area.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 7.2 shows Access Units and Bus Operations.
Table 7.1
Note:
Table 7.2
SFR/Data flash
Program ROM/RAM
Bus
1. Data flash is provided only in the following four: the R8C/L35A Group, L36A Group, L38A Group,
Even address
Even address
Odd address
Word access
Word access
Odd address
Byte access
Byte access
and L3AA Group.
Area
Bus Cycles by Access Area
Access Units and Bus Operations
Access Area
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
Oct 30, 2009
SFR, Data flash
Even
Odd
Data
Data
Even
Odd
2 cycles of CPU clock
1 cycle of CPU clock
Even + 1
Odd + 1
Data
Data
Data
Data
Bus Cycle
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
ROM (program ROM), RAM
Even
Even
Odd
Odd
Data
Data
Data
Data
Even + 1
Odd + 1
Data
Data
7. Bus