R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 804

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 767 of 802
Figure 35.5
When the value of the buffer register is set to 0000h:
Transfer takes place at compare match between registers TRD0 and TRDGRA0.
After this, when the buffer register is set to 0001h or above and a value than smaller the value of the
TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time
after setting, the value is transferred to the general register. After that, the value is transferred with the timing
selected by bits CMD0 and CMD1.
TRDGRD0 register
TRDGRB0 register
TRDIOD0 output
TRDIOB0 output
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at TRD1 register underflow
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase).
in PWM mode).
Operation when Buffer Register Value Is Set to 0000h in Complementary PWM Mode
0000h
m+1
n2
n1
Oct 30, 2009
Transfer with timing
set by bits CMD1 to
CMD0
n2
Transfer
n1
n1
Transfer
0000h
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
content of TRDGRD0
register is set to
0000h.
0000h
m: Value set in TRDGRA0 register
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
of first setting to
0001h n1 < m
n1
Transfer
n1
TRD0 register count value
Transfer with timing
set by bits CMD1 to
CMD0
Transfer
TRD1 register count value
35. Usage Notes