R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 397

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 360 of 802
20.5.10 Timer RD Output Control Register (TRDOCR) in PWM Mode
Note:
20.5.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in PWM Mode
Notes:
1. If the pin function is set for waveform output (refer to 6.6 Port Settings ), the initial output level is output when the
1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the
2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.
3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 013Dh
Address 0140h (TRDCR0), 0150h (TRDCR1)
TRDOCR register is set.
Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to
0 (count stops).
TRDFCR register is 1 (external clock input enabled).
0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Symbol
Symbol
Symbol
Symbol
CKEG0 External clock edge select bit
CKEG1
CCLR0 TRDi counter clear select bit
CCLR1
CCLR2
Bit
Bit
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
TCK0
TCK1
TCK2
CCLR2
TOD1
b7
b7
0
0
TRDIOA0 output level select bit
TRDIOB0 output level select bit
TRDIOC0 initial output level select bit
TRDIOD0 initial output level select bit
TRDIOA1 initial output level select bit
TRDIOB1 initial output level select bit
TRDIOC1 initial output level select bit
TRDIOD1 initial output level select bit
Count source select bit
CCLR1
TOC1
b6
b6
0
0
Oct 30, 2009
Bit Name
Bit Name
CCLR0
TOB1
b5
b5
0
0
CKEG1
TOA1
(3)
b4
b4
0
0
(1)
b2 b1 b0
b4 b3
Set to 001b (TRDi register cleared by compare match
with TRDGRAi register) in PWM mode.
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRDCLK input
1 1 0: Do not set.
1 1 1: Do not set.
0 0: Count at the rising edge
0 1: Count at the falling edge
1 0: Count at both edges
1 1: Do not set.
(1)
(1)
(1)
(1)
(1)
CKEG0
TOD0
b3
b3
0
0
Set to 0 (output enabled) in PWM mode.
0: Initial output is inactive level
1: Initial output is active level
Set this bit to 0 (output enabled) in PWM mode. R/W
0: Inactive level
1: Active level
TOC0
TCK2
b2
b2
0
0
(1)
Function
or fC2
TOB0
TCK1
Function
b1
b1
0
0
(2)
TOA0
TCK0
b0
b0
0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W