R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 328

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 291 of 802
Figure 19.12
Figure 19.12 shows an Operating Example When TRCGRC Register is Used for Output Control of TRCIOA
Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin.
TRCSR register
TRCSR register
TRCSR register
TRCSR register
TRCIOA output
TRCIOB output
The above applies under the following conditions:
Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer registers).
Bits EA and EB in the TRCOER register are set to 0 (TRCIOA and TRCIOB pin output enabled).
The CCLR bit in the TRCCR1 register are set to 1 (TRC register is set to 0000h by compare match with the TRCGRA register).
Bits TOA and TOB in the TRCCR1 register are set to 0 (initial output at low until compare match).
Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted by TRCGRA register compare match).
Bits IOB2 to IOB0 in the TRCIOR0 register are set to 011b (TRCIOB output inverted by TRCGRB register compare match).
Bits IOC2 to IOC0 in the TRCIOR1 register are set to 011b (TRCIOA output inverted by TRCGRC register compare match).
The IOC3 bit in the TRCIOR1 register are set to 0 (TRCIOA output register).
Bits IOD2 to IOD0 in the TRCIOR1 register are set to 011b (TRCIOB output inverted by TRCGRD register compare match).
The IOD3 bit in the TRCIOR1 register are set to 0 (TRCIOB output register).
The CSEL bit in the TRCCR2 register are set to 0 (TRC count continues after compare match).
IMFC bit in
IMFD bit in
IMFA bit in
IMFB bit in
Count source
Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin
Operating Example When TRCGRC Register is Used for Output Control of TRCIOA
TRC register value
FFFFh
0000h
Initial output “L”
1
0
1
0
Initial output “L”
1
0
1
0
m
n
p
q
Output inverted by compare match
Oct 30, 2009
Set to 0 by a program.
Output inverted by compare match
Set to 0 by a program.
q+1
p+1
n+1
p-q
m+1
Set to 0 by a program.
m: Value set in TRCGRA register
n: Value set in TRCGRC register
p: Value set in TRCGRB register
q: Value set in TRCGRD register
Set to 0 by a program.
m-n
19. Timer RC