R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 155

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 118 of 802
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions.
(Refer to Figure 8.1 Clock Generation Circuit.)
The system clock is the clock source for the CPU and peripheral function clocks. The XIN clock, XCIN clock,
or on-chip oscillator clock can be selected.
The CPU clock is an operating clock for the CPU and the watchdog timer.
The system clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. The division ratio can be
selected by the CM06 bit in the CM0 register and bits CM16 and CM17 in the CM1 register.
Use the XCIN clock while the XCIN clock oscillation stabilizes.
After a reset, the low-speed on-chip oscillator clock divided by 1 (no division) is used as the CPU clock.
When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). To enter stop mode, set the
CM35 bit in the CM3 register to 0 (settings of CM06 in CM0 register and bits CM16 and CM17 in CM1
register enabled).
The peripheral function clock is an operating clock for the peripheral functions.
The fi (i = 1, 2, 4, 8, and 32) clock is generated by the system clock divided by i. It is used for timers RA, RB,
RC, RD, RE, RG, the serial interface, the A/D converter, and the LCD waveform control circuit.
When the MCU enters wait mode after bits CM02 to CM01 in the CM0 register are set to 01, 10, or 11, the fi
clock stops.
This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (low-
speed on-chip oscillator on).
In wait mode, the fOCO-S clock does not stop.
fOCO128 clock is generated by fOCO-S divided by 128.
fOCO128 is configured as the capture signal used in the TRCGRA register for timer RC and timer RD0 for
timer RD.
fC-LCD is used in the LCD waveform control circuit.
Use this clock only while the XCIN clock oscillation stabilizes.
CPU Clock and Peripheral Function Clock
System Clock
CPU Clock
Peripheral Function Clock (f1, f2, f4, f8, and f32)
fOCO-S
fOCO128
fC-LCD
Oct 30, 2009
8. Clock Generation Circuit