R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 551

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 514 of 802
Figure 24.3
S2RIC register
U2C1 register
U2C1 register
U2C1 register
(1) Transmit Timing Example (Internal Clock Selected)
(2) Receive Timing Example (External Clock Selected)
U2RB register
U2C1 register
The above applies under the following conditions:
The above applies under the following conditions:
Transfer clock
fEXT: Frequency of external clock
S2TIC register
U2C1 register
U2C1 register
TXEPT flag in
U2C0 register
OER flag in
• CKDIR bit in U2MR register = 0 (internal clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• CKPOL bit in U2C0 register = 0
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty)
• CKDIR bit in U2MR register = 1 (external clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1 (RTS function selected)
• CKPOL bit in U2C0 register = 0
(transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
(transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
RE bit in
TE bit in
RI bit in
TI bit in
IR bit in
TE bit in
RXD2
RTS2
IR bit in
CLK2
TI bit in
CTS2
TXD2
CLK2
“H”
“L”
1
0
1
0
1
0
1
0
1
0
1
0
“H”
“L”
1
0
1
0
1
0
1
0
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data transfer from UART2 receive register
to U2RB register
Data set in U2TB register
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Dummy data set in U2TB register
Data transfer from U2TB register to UART2 transmit register
Oct 30, 2009
Set to 0 when an interrupt request is acknowledged or by a program.
TCLK
1/fEXT
Received data capture
TC
Data transfer from U2TB register to UART2 transmit register
Data read from U2RB register
Pulsing stops because CTS2 is “H”.
D0 D1 D2 D3 D4 D5
Set to 0 when an interrupt request is acknowledged or by a program.
“L” by reading U2RB register
D0 D1 D2 D3 D4 D5 D6 D7
D6
D7
Make sure the following conditions are met when
the CLK2 pin input is high before receiving data:
• TE bit in U2C0 register = 1 (transmission enabled)
• RE bit in U2C1 register = 1 (reception enabled)
• Dummy data write to the U2TB register
D0 D1 D2 D3 D4 D5
TC = TCLK = 2(n+1)/fj
n: Value set in U2BRG register
Pulsing stops because TE bit is set to 0.
fj: Frequency of U2BRG count source
D0 D1 D2 D3 D4 D5 D6 D7
(f1, f8, f32, fC)
24. Serial Interface (UART2)
D6