R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 485

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 448 of 802
22.2.3
Note:
1. In phase counting mode, the settings of bits TCK0 to TCK2 and bits CKEG0 and CKEG1 are disabled and
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0172h
the operation of phase counting mode has priority.
Symbol
Symbol
CKEG0 External clock active edge
CKEG1
CCLR0 TRG register clear source
CCLR1
Bit
TCK0
TCK1
TCK2
Timer RG Control Register (TRGCR)
—
b7
—
1
Count source select bit
select bit
select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
CCLR1
b6
(1)
0
Bit Name
Oct 30, 2009
CCLR0
b5
0
(1)
CKEG1
b4
0
b2 b1 b0
b4 b3
b6 b5
0 0 0: f1
0 0 1: Do not set.
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRGCLKA input
1 1 0: Do not set.
1 1 1: TRGCLKB input
0 0: Count at the rising edge
0 1: Count at the falling edge
1 0: Count at both the rising/falling edges
1 1: Do not set.
0 0: Clear disabled
0 1: TRG register cleared by input capture or
1 0: TRG register cleared by input capture or
1 1: Do not set.
compare match with TRGGRA register
compare match with TRGGRB register
CKEG0
b3
0
TCK2
b2
0
Function
TCK1
b1
0
TCK0
b0
0
22. Timer RG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—