R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 386

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 349 of 802
Figure 20.11
20.4.20 Operating Example
TRDSTR register
TRDSRi register
TRDSRi register
TRDSRi register
TRDIOBi output
TRDIOCi output
TRDIOAi output
TSTARTi bit in
The above applies under the following conditions:
The CSELi bit in the TRDSTR register is set to 1 (TRDi register count continues after compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).
Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (TRDIOAi, TRDIOBi and TRDIOCi pin output enabled).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (TRDi register is set to 000h by compare match with the TRDGRAi register).
Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output at low until compare match), the TOCi bit is set to 1 (initial output at high until compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted by TRDGRAi register compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi high-level output at TRDGRBi register compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi low-level output at TRDGRCi register compare match).
The IOD3 bit in the TRDIORCi register is set to 1 (TRDGRDi register does not control TRDIOBi pin output).
i = 0 or 1
IMFC bit in
IMFA bit in
IMFB bit in
Count source
TRDi register value
1
0
1
0
1
0
Operating Example of Output Compare Function
1
0
m
m
n
n
p
p
Initial output “H”
Initial output “L”
Initial output “L”
P+1
n+1
Oct 30, 2009
m+1
“L” output at compare match
M: Value set in TRDGRAi register
n: Value set in TRDGRBi register
p: Value set in TRDGRCi register
Set to 0 by a program.
“H” output at compare match
Set to 0 by a program.
Output inverted by compare match
Set to 0 by a program.
m+1
Count
stops
Output level
Output level
Output level
held
held
held
restarts
Count
20. Timer RD