R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 313

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 276 of 802
19.3.4
When using the timer mode’s output compare function, PWM mode, or PWM2 mode, pulse output from the
TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a
programmable I/O port by means of input to the INT0 pin.
A pin used for output by the timer mode’s output compare function, PWM mode, or PWM2 mode can be set to
function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output enabled).
If a low-level signal is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output
forced cutoff signal input INT0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1
(timer RC output disabled, TRCIOj output pin functions as a programmable I/O port). When one or two cycles
of the timer RC operation clock after a low-level signal input to the INT0 pin (refer to Table 19.1 Timer RC
Operating Clocks) has elapsed, the TRCIOj output pin functions as a programmable I/O port.
Make the following settings to use this function.
• Set the pin state following forced cutoff of pulse output (high impedance (input), low-level output, or high-
• Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register.
• Set the direction registers for the I/O ports selected as INT0 to input mode:
• Select the INT0 digital filter with bits INT0F0 and INT0F1 in the INTF register.
• Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled).
The IR bit in the INT0IC register is set to 1 (interrupt requested) in accordance with the setting of the POL bit
and a change in the INT0 pin input (refer to 11.8 Notes on Interrupts).
For details on interrupts, refer to 11. Interrupts.
level output). (Refer to 6. I/O Ports.)
When INT0 is assigned to P3_0 by the INT0SEL0 bit in the INTSR register, set the PD3_0 bit in the PD3
register to 0 (input mode).
When INT0 is assigned to P11_0 by the INT0SEL0 bit in the INTSR register, set the PD11_0 bit in the PD11
register to 0 (input mode).
Forced Cutoff of Pulse Output
Oct 30, 2009
19. Timer RC