R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 572

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 535 of 802
24.5.3
24.5.4
24.5.5
24.5.6
The transfer clock is used to transmit and receive data as is shown in Figure 24.14 Transfer to U2RB Register
and Interrupt Timing.
The CSC bit in the U2SMR2 register is used to synchronize an internally generated clock (internal SCL2) and
an external clock supplied to the SCL2 pin. When the CSC bit is set to 1 (clock synchronization enabled), if a
falling edge on the SCL2 pin is detected while the internal SCL2 is high, the internal SCL2 goes low. The value
of the U2BRG register is reloaded and counting of the low-level intervals starts. When the internal SCL2
changes state from low to high while the SCL2 pin is low, counting stops. When the SCL2 pin goes high,
counting restarts. In this way, the UART2 transfer clock is equivalent to AND of the internal SCL2 and the
clock signal applied to the SCL2 pin. The transfer clock works from a half cycle before the falling edge of the
internal SCL2 1st bit to the rising edge of the 9th bit. To use this function, select an internal clock for the
transfer clock.
The SWC bit in the U2SMR2 register can be used to select whether the SCL2 pin is fixed low or freed from
low-level output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the U2SMR4 register is set to 1 (enabled), SCL2 output is turned off (placed in the high
impedance state) when a stop condition is detected.
Setting the SWC2 bit in the U2SMR2 register to 1 (low-level output) allows a low-level signal to be forcibly
output from the SCL2 pin even during transmission or reception. Setting the SWC2 bit to 0 (transfer clock)
allows the transfer clock to be output from or supplied to the SCL2 pin, instead of outputting a low-level signal.
If the SWC9 bit in the U2SMR4 register is set to 1 (SCL hold low enabled) when the CKPH bit in the U2SMR3
register is 1, the SCL2 pin is fixed low at the falling edge of the clock pulse next to the 9th. Setting the SWC9
bit to 0 (SCL hold low disabled) frees the SCL2 pin from low-level output.
The data written to bits b7 to b0 (D7 to D0) in the U2TB register is output in descending order from D7.
The 9th bit (D8) is ACK or NACK.
Set the initial value of SDA2 transmit output when IICM is set to 1 (I
U2MR register are set to 000b (serial interface disabled).
Bits DL2 to DL0 in the U2SMR3 register allow addition of no delays or a delay of two to eight U2BRG count
source clock cycles to the SDA2 output.
Setting the SDHI bit in the U2SMR2 register to 1 (SDA output disabled) forcibly places the SDA2 pin in the
high impedance state. Do not write to the SDHI bit at the rising edge of the UART2 transfer clock.
When the IICM2 bit is set to 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits b7 to b0 in the
U2RB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit is set to 1, the 1st to 7th bits (D7 to D1) of received data are stored in bits b6 to b0 in the
U2RB register and the 8th bit (D0) is stored in bit b8 in the U2RB register. Even when the IICM2 bit is set to 1,
if the CKPH bit is 1, the same data as when the IICM2 bit is 0 can be read by reading the U2RB register after
the rising edge of the 9th bit of the clock.
When the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not output) and the ACKC
bit in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the U2SMR4 register is
output from the SDA2 pin.
When the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the
rising edge of the 9th bit of the transmit clock. An ACK interrupt request is generated if the SDA2 pin is low at
the rising edge of the 9th bit of the transmit clock.
When ACK2 (UART2 reception) is selected to generate a DTC request source, a DTC transfer can be activated
by detection of an acknowledge.
Transfer Clock
SDA Output
SDA Input
ACK and NACK
Oct 30, 2009
2
C mode) and bits SMD2 to SMD0 in the
24. Serial Interface (UART2)