R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 462

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 425 of 802
Figure 20.27
•
Using bits CMD1 to CMD0, select the timing of data transfer from the buffer register to the general register.
However, transfer takes place with the following timing in spite of the values of bits CMD1 to CMD0 in the
following cases:
Buffer register value
Transfer takes place at underflow of the TRD1 register.
After this, when the buffer register is set to 0001h or above and a value smaller than the value of the
TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is transferred
to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0.
TRDGRD0 register
TRDGRB0 register
TRDIOD0 output
TRDIOB0 output
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase).
PWM Mode
Operation when Buffer Register Value
between registers TRD0 and TRDGRA0 in complementary PWM mode).
Transfer with timing set by
bits CMD1 to CMD0
0000h
m+1
n3
n2
n1
TRDGRA0 register value:
Oct 30, 2009
Transfer
n2
n1
n2
Transfer at TRD1
register underflow
because of n3 > m
n3
Transfer
n3
Transfer at TRD1
register underflow
because of first
setting to n2 < m
Transfer
n2
m: Value set in TRDGRA0 register
TRDGRA0 Register Value in Complementary
n2
n1
Transfer with timing set by
bits CMD1 to CMD0
Transfer
n1
TRD0 register count value
TRD1 register count value
20. Timer RD