R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 196

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 159 of 802
Figure 11.5
11.3.7
Address
m+1
m 4
m 3
m 2
m 1
m
Stack state before interrupt request acknowledgement
MSB
In the interrupt sequence, the FLG register and PC are saved on the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved on the stack, the 16 low-order bits in the PC are saved.
Figure 11.5 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers should be saved by a program at the beginning of the interrupt routine. The
PUSHM instruction can save several registers in the register bank being currently used
instruction.
Note:
Previous stack contents
Previous stack contents
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Saving Registers
Stack
Stack State Before and After Acknowledgement of Interrupt Request
Note:
1. When an INT instruction for software numbers 32 to 63 has been executed,
this SP is indicated by the U flag. Otherwise it is ISP.
LSB
Oct 30, 2009
[SP]
SP value before
interrupt request
acknowledgement
(1)
Address
m 4
m 3
m 2
m 1
m+1
m
Stack state after interrupt request acknowledgement
MSB
Previous stack contents
Previous stack contents
FLGH
FLGL
PCM
PCL
Stack
PCH
LSB
PCL
PCM
PCH
FLGL
FLGH
[SP]
New SP value
: 8 low-order bits of PC
: 8 middle-order bits of PC
: 4 high-order bits of PC
: 8 low-order bits of FLG
: 4 high-order bits of FLG
(1)
(1)
with a single
11. Interrupts