R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 446

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 409 of 802
20.8.9
Note:
1. If the pin function is set for waveform output (refer to 6.6 Port Settings ), the initial output level is output when the
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 013Dh
TRDOCR register is set.
Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0
(count stops).
Symbol
Symbol
Bit
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
Timer RD Output Control Register (TRDOCR) in PWM3 Mode
TOD1
b7
0
TRDIOA0 output level select bit
TRDIOB0 output level select bit
TRDIOC0 initial output level select bit Disabled in PWM3 mode.
TRDIOD0 initial output level select bit
TRDIOA1 initial output level select bit
TRDIOB1 initial output level select bit
TRDIOC1 initial output level select bit
TRDIOD1 initial output level select bit
TOC1
b6
0
Oct 30, 2009
Bit Name
TOB1
b5
0
TOA1
b4
0
(1)
(1)
0: Active level is high,
1: Active level is low,
0: Active level is high,
1: Active level is low,
TOD0
b3
initial output at low,
high-level output at compare match with
the TRDGRA1 register,
low-level output at compare match with
the TRDGRA0 register
initial output at high,
low-level output at compare match with
the TRDGRA1 register,
high-level output at compare match with
the TRDGRA0 register
initial output at low,
high-level output at compare match with
the TRDGRB1register,
low-level output at compare match with
the TRDGRB0 register
initial output at high,
low-level output at compare match with
the TRDGRB1 register,
high-level output at compare match with
the TRDGRB0 register
0
TOC0
b2
0
Function
TOB0
b1
0
TOA0
b0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W