R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 613

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 576 of 802
Figure 26.13
26.5.4
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode) and the CSS1 bit is
set to 1 (function as the SCS output pin), set the MSS bit in the SSCRH register to 1 (operation as the master
device) and check the arbitration of the SCS pin before starting serial transfer. If the synchronous serial
communication unit detects that the synchronized internal SCS signal is held low in this period, the CE bit in
the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operation as a slave
device).
Figure 26.13 shows the Arbitration Check Timing.
Future transmit operations are not performed while the CE bit is set to 1. Set the CE bit to 0 (no conflict error)
before starting transmission.
(synchronization)
SSCRH register
Transfer start
Internal SCS
SCS Pin Control and Arbitration
SCS output
MSS bit in
SCS input
Arbitration Check Timing
CE
1
0
Oct 30, 2009
High-impedance
During arbitration detection
Write data to
the SSTDR register.
26. Synchronous Serial Communication Unit (SSU)
Maximum time of SCS internal
synchronization