R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 810

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 773 of 802
35.14.2 Clock Asynchronous Serial I/O (UART) Mode
35.14.3 Special Mode 1 (I
35.14.2.1 Transmission/Reception
35.14.2.2 Transmission
When the RTS function is used with an external clock, the RTS2 pin outputs a low-level signal, which informs
the transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs a high-level signal
when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by
connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an
internal clock is selected.
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at
the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set to 1
(transmit data output at the rising edge and receive data input at the falling edge of the transfer clock).
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To generate start, stop, and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0 and wait for
more than half cycle of the transfer clock before changing each condition generation bit (STAREQ, RSTAREQ,
and STPREQ) from 0 to 1.
The TE bit in the U2C1 register is set to 1 (transmission enabled)
The TI bit in the U2C1 register is set to 0 (data in the U2TB register)
If the CTS function is selected, input on the CTS2 pin is low.
Oct 30, 2009
2
C Mode)
35. Usage Notes