R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 193

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 156 of 802
Table 11.3
11.3
000b
001b
010b
011b
100b
101b
110b
111b
Bits ILVL2 to ILVL0
11.3.1
11.3.2
11.3.3
The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority.
This description does not apply to non-maskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register
to enable or disable a maskable interrupt. Whether an interrupt is requested or not is indicated by the IR bit in
the corresponding interrupt control register.
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. After the interrupt request is
acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (no interrupt
requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RC interrupt, the timer RD interrupt, the synchronous serial
communication unit interrupt the I
to 11.7 Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication Unit, I
Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources).
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 11.3 lists the Settings of Interrupt Priority Levels and Table 11.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are the conditions when an interrupt is acknowledged:
•
•
•
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
I flag = 1
IR bit = 1
Interrupt priority level > IPL
Interrupt Control
I Flag
IR Bit
Bits ILVL2 to ILVL0, IPL
Settings of Interrupt Priority
Levels
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Interrupt Priority Level
Oct 30, 2009
2
C bus interface interrupt, and the flash memory interrupt are different. Refer
Priority
High
Low
Table 11.4
000b
001b
010b
011b
100b
101b
110b
111b
IPL
IPL
Interrupt Priority Levels Enabled by
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
All maskable interrupts disabled
Enabled Interrupt Priority Level
11. Interrupts
2
C bus