R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 437

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 400 of 802
Figure 20.21
Bits TSTART0 and TSTART1
in TRDSTR register
TRDGRB0 register
TRDGRD0 register
TRDSR1 register
TRDSR0 register
TRDSR0 register
TRDIOD0 output
TRDIOC0 output
TRDIOB0 output
IMFA bit in
IMFB bit in
UDF bit in
Count source
Operating Example in Complementary PWM Mode
TRDi register value
0000h
m+1
CMD0, CMD1: Bits in TRDFCR register
i = 0 or 1
The above applies under the following condition:
Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level at high, active level is low for normal-phase and counter-phase)
1
0
1
0
1
0
1
0
m
n
p
Initial output “H”
Initial output “H”
Oct 30, 2009
Transfer (when bits CMD1 to CMD0 are set to 11b)
Active level “L”
n+1
n
n+1-p
m+2-p
n
p
m-p-n+1
Set to 0 by a program.
phase active level
Width of normal-
(m-p-n+1)
2
Set to 0 by a program.
Dead
time
p
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register
p: Value set in TRD0 register
Width of counter-phase active level
Transfer (when bits CMD1 to CMD0
are set to 10b)
TRD0 register value
n
TRD1 register value
Change by a program.
(n+1-p)
Set to 0 by a program.
n+1-p
Next data
2
FFFFh is set.
20. Timer RD