R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 233

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 196 of 802
14.3.2
Table 14.2
Notes:
Count source
Count operation
Period
Watchdog timer
initialization conditions
Count start conditions
Count stop condition
Operations at underflow
The count source for the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 14.2 lists the Watchdog Timer Specifications (Count Source Protection Mode Disabled).
1. The watchdog timer is initialized when 00h and then FFh is written to the WDTR register. The
2. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh
3. Write the WDTR register during the count operation of the watchdog timer.
prescaler is initialized after a reset. This may cause some errors due to the prescaler during the
watchdog timer period.
with a flash programmer.
Count Source Protection Mode Disabled
Item
Watchdog Timer Specifications (Count Source Protection Mode Disabled)
CPU clock
Decrement
Division ratio of prescaler (n) × count value of watchdog timer (m)
n: 16 or 128 (selected by the WDTC7 bit in the WDTC register), or
m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register
Example:
The period is approximately 13.1 ms when:
- The CPU clock frequency is set to 20 MHz.
- The prescaler is divided by 16.
- Bits WDTUFS1 to WDTUFS0 are set to 11b (3FFFh).
• Reset
• Write 00h and then FFh to the WDTR register.
• Underflow
The operation of the watchdog timer after a reset is selected by
the WDTON bit
• When the WDTON bit is set to 1 (watchdog timer is stopped after reset).
• When the WDTON bit is set to 0 (watchdog timer starts automatically after
Stop mode, wait mode (Count resumes from the retained value after exiting.)
• When the PM12 bit in the PM1 register is set to 0.
• When the PM12 bit in the PM1 register is set to 1.
Oct 30, 2009
The watchdog timer and prescaler are stopped after a reset and
start counting when the WDTS register is written to.
reset).
The watchdog timer and prescaler start counting automatically after a reset.
Watchdog timer interrupt
Watchdog timer reset (refer to 5.3 Watchdog Timer Reset )
2 when the low-speed clock is selected (CM07 bit in CM0 register = 1)
(2)
in the OFS register (address 0FFFFh).
CPU clock
Specification
(3)
14. Watchdog Timer
(1)