R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 552

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 515 of 802
Figure 24.4
24.3.1
24.3.2
(1) CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
(2) CKPOL bit in U2C0 register = 1 (transmit data output at the rising edge and
CLK2
TXD2
RXD2
CLK2
TXD2
RXD2
The above applies under the following conditions:
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow
the procedures below:
• Resetting the U2RB register
(1) Set the RE bit in the U2C1 register to 0 (reception disabled).
(2) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode).
(4) Set the RE bit in the U2C1 register to 1 (reception enabled).
• Resetting the U2TB register
(1) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled).
(2) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode).
(3) Write 1 to the TE bit in the U2C1 register (transmission enabled), regardless of the TE bit value of the
The CKPOL bit in the U2C0 register can be used to select the transfer clock polarity. Figure 24.4 shows the
Transfer Clock Polarity.
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (not inverted)
receive data input at the rising edge of the transfer clock)
receive data input at the falling edge of the transfer clock)
U2C2 register.
Measure for Dealing with Communication Errors
CLK Polarity Select Function
Transfer Clock Polarity
D0
D0
D0
D0
Oct 30, 2009
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
Low-level output from the CLK2 pin
during no transfer
High-level output from the CLK2 pin
during no transfer
24. Serial Interface (UART2)