R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 380

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 343 of 802
20.4.13 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) for Output
Notes:
1. To select 1 (TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
2. To select 1 (TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0142h (TRDIORC0), 0152h (TRDIORC1)
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the
TRDIORAi register.
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the
TRDIORAi register.
Symbol
Symbol
Bit
IOC0
IOC1
IOC2
IOC3
IOD0
IOD1
IOD2
IOD3
Compare Function
IOD3
b7
1
TRDGRC control bit
TRDGRC mode select bit
TRDGRC register function select bit 0: TRDIOA output register
TRDGRD control bit
TRDGRD mode select bit
TRDGRD register function select bit 0: TRDIOB output register
IOD2
b6
0
Oct 30, 2009
Bit Name
IOD1
b5
0
(1)
(2)
IOD0
b4
0
b1 b0
Set to 0 (output compare) for the output compare
function.
1: General register or buffer register
b5 b4
Set to 0 (output compare) for the output compare
function.
1: General register or buffer register
0 0: Pin output by compare match is disabled
0 1: Low-level output at compare match with
1 0: High-level output at compare match with
1 1: Toggle output at compare match with
0 0: Pin output by compare match is disabled
0 1: Low-level output at compare match with
1 0: High-level output at compare match with
1 1: Toggle output at compare match with
IOC3
(Refer to 20.4.21 Changing Output Pins in
Registers TRDGRCi (i = 0 or 1) and TRDGRDi .)
(Refer to 20.4.21 Changing Output Pins in
Registers TRDGRCi (i = 0 or 1) and TRDGRDi .)
b3
1
the TRDGRCi register
the TRDGRCi register
the TRDGRCi register
the TRDGRDi register
the TRDGRDi register
the TRDGRDi register
IOC2
b2
0
Function
IOC1
b1
0
IOC0
b0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W