R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 348

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 311 of 802
Figure 20.3
20.2.2
Table 20.4
i = 0 or 1
Input capture function
Output compare function Compare match between the TRDi
PWM mode
Reset synchronous PWM
mode
Complementary PWM
mode
PWM3 mode
Function and Mode
The TRDGRCi (i = 0 or 1) register can be used as the buffer register of the TRDGRAi register, and the
TRDGRDi register can be used as the buffer register of the TRDGRBi register by means of bits BFCi and BFDi
in the TRDMR register.
• Buffer register of TRDGRAi: TRDGRCi register
• Buffer register of TRDGRBi: TRDGRDi register
Buffer operation depends on the mode.
Table 20.4 lists the Buffer Operation in Each Mode.
Buffer Operation
i = 0 or 1
The above applies under the following conditions:
• The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 100b (input capture at the falling edge).
the TRDGRAi register).
Buffer Operation in Each Mode
Buffer Operation of Input Capture Function
TRDGRAi register
TRDGRCi register
TRDIOAi input
TRDi register
TRDIOAi input
(input capture signal)
TRDGRCi register
Input capture signal input
register and the TRDGRAi
(TRDGRBi) register
Compare match between the TRD0
register and the TRDGRA0 register
• Compare match between the TRD0
• TRD1 register underflow
Compare match between the TRD0
register and the TRDGRA0 register
(buffer)
Oct 30, 2009
register and the TRDGRA0 register
(buffer)
Transfer Timing
n-1
m
TRDGRAi
register
n
The content of the TRDGRAi
(TRDGRBi) register is transferred to
the buffer register.
The content of the buffer register is
transferred to the TRDGRAi
(TRDGRBi) register.
The content of the buffer register is
transferred to the TRDGRAi
(TRDGRBi) register.
The content of the buffer register is
transferred to registers TRDGRB0,
TRDGRA1, and TRDGRB1.
The content of the buffer register is
transferred to registers TRDGRA0,
TRDGRB0, TRDGRA1, and
TRDGRB1.
Transfer
Transfer
m
n
Transfer Register
n+1
TRDi
20. Timer RD