R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 620

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 583 of 802
27.2.4
27.2.5
b7 to b0
b7 to b0
After Reset
After Reset
Bit
Bit
Address 0194h
Address 0196h
Symbol
Symbol
Bit
Bit
This register stores transmit data.
When the ICDRS register is detected as empty, the stored transmit data is transferred to the ICDRS
register and transmission starts.
When the next transmit data is written to the ICDRT register during the data transmission from the
ICDRS register, continuous transmission is enabled.
When the MLS bit in the ICMR register is set to 1 (data transfer with LSB first), the MSB-LSB
inverted data is read after writing to the ICDRT register.
This register stores receive data.
When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR
register and the next receive operation is enabled.
IIC bus Transmit Data Register (ICDRT)
IIC bus Receive Data Register (ICDRR)
b7
b7
—
—
1
1
b6
b6
—
—
1
1
Oct 30, 2009
b5
—
b5
—
1
1
b4
b4
—
—
1
1
Function
Function
b3
b3
—
—
1
1
b2
b2
—
—
1
1
b1
b1
—
—
1
1
b0
b0
—
—
1
1
27. I
2
C bus Interface
R/W
R/W
R/W
R