R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 861

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

RENESAS TECHNICAL UPDATE TN-R8C-A007A/E
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Note on digital filter
When the interrupt source is an input that uses a digital filter, note the following in the procedure when changing the
Note on timer RB
(The R8C/1x Series does not have timer RB.)
When selecting timer RA underflow as the timer RB count source, set timer RA to timer mode, pulse output mode, or
event counter mode.
Note on timer Y
(The R8C/2x Series, R8C/3x Series, and R8C/Lx Series do not have timer Y.)
When selecting timer X underflow as the timer Y count source, set timer X to timer mode, pulse output mode, or event
counter mode.
Notes on UARTi (i = 0 to 2)
(The value for i varies according to the MCU.)
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interrupt source.
After changing the interrupt source, wait for three or more cycles of the digital filter sampling clock before setting the
corresponding IR bit to 0 (no interrupt request). For more information on the instructions used to set the IR bit to 0 and
related notes, refer to Rewriting Interrupt Control Register.
When setting bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled), set the TE bit in the UiC1
register to 0 (transmission
disabled) and the RE bit to 0 (reception disabled).
When bits SMD2 to SMD0 in the UiMR register are 001b (clock synchronous serial I/O mode), bits FER, PER, and
SUM (error flags) in the UiRB register are disabled. When read, the read value is undefined.
If communication is ended prematurely or a communication error occurs while transmitting or receiving in clock
synchronous serial I/O mode, and communication is performed again, follow the steps below:
If communication is ended prematurely or a communication error occurs while transmitting or receiving in UART mode,
and communication is performed again, follow the steps below:
(1) Set the TE bit in the UiC1 register to 0 (transmission disabled) and the RE bit to 0 (reception disabled).
(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode).
(4) Set the TE bit in the UiC1 register to 1 (transmission enabled) and the RE bit to 1 (reception enabled).
(1) Set the TE bit in the UiC1 register to 0 (transmission disabled) and the RE bit to 0 (reception disabled).
(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the UiMR register to 100b (UART mode, transfer data 7 bits long), 101b
(4) Set the TE bit in the UiC1 register to 1 (transmission enabled) and the RE bit to 1 (reception enabled).
(UART mode, transfer data 8 bits long), or 110b (UART mode, transfer data 9 bits long).
Date: Sep.25, 2009
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