R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 326

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 289 of 802
Figure 19.10
19.5.5
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOC output
TRCIOA output
TRCIOB output
TSTART bit in
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer registers).
• Bits EA, EB, and EC in the TRCOER register are set to 0 (TRCIOA, TRCIOB, and TRCIOC pin output enabled).
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register is set to 0000h by compare match with TRCGRA register ).
• Bits TOA and TOB in the TRCCR1 register are are set to 0 (initial output at low until compare match) and
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted by TRCGRA compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (TRCIOB high-level output at TRCGRB compare match).
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (TRCIOC low-level output at TRCGRC compare match).
• The CSEL bit in the TRCCR2 register is set to 0 (TRC count continues after TRCGRA compare match).
the TOC bit is set to 1 (initial output at high until compare match).
IMFA bit in
IMFB bit in
IMFC bit in
Operating Example
Count source
TRC register value
Operating Example of Output Compare Function
1
0
1
0
1
0
1
0
m
n
p
Initial output “H”
Oct 30, 2009
Initial output “L”
Initial output “L”
P+1
n+1
m+1
“L” output at compare match
Set to 0 by a program.
compare match
“H” output at
Set to 0 by a program.
m: Value set in TRCGRA register
n: Value set in TRCGRB register
p: Value set in TRCGRC register
Output inverted at
compare match
Set to 0 by a program.
m+1
Output level held
Output level held
Output level held
Count
stops
restarts
Count
19. Timer RC