R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 391

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 354 of 802
Table 20.9
i = 0 or 1
j = either B, C, or D
h = either A, B, C, or D
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOA1 pin function
TRDIOB0, TRDIOC0, TRDIOD0,
TRDIOB1, TRDIOC1, TRDIOD1
pins function
INT0 pin function
Read from timer
Write to timer
Selectable functions
PWM Mode Specifications
Item
Oct 30, 2009
f1, f2, f4, f8, f32, or
PWM period: 1/fk x (m+1)
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register
Programmable I/O port, pulse output forced cutoff signal input, or INT0
The count value can be read by reading the TRDi register.
The value can be written to the TRDi register.
• One to three PWM output pins selectable per timer RDi
external signal input to the TRDCLK pin (active edge selectable by a
program)
Increment
Active level width: 1/fk x (m-n)
Inactive level width: 1/fk x (n+1)
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
• When the CSELi bit in the TRDSTR register is set to 0, the count
• Compare match (the contents of the TRDi register and the TRDGRhi
• TRDi register overflow
Programmable I/O port or TRDCLK (external clock) input
Programmable I/O port
Programmable I/O port or pulse output
(selectable for each individual pin)
interrupt input
• Active level selectable for each individual pin.
• Initial output level selectable for each individual pin.
• Synchronous operation (Refer to 20.2.3 Synchronous Operation .)
• Buffer operation (Refer to 20.2.2 Buffer Operation .)
• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse Output
• A/D trigger generation
fk: Frequency of count source
m: Value set in TRDGRAi register
n: Value set in TRDGRji register
when the CSELi bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops.
stops at the compare match with the TRDGRAi register.
The PWM output pin holds the level after the output changes by the
compare match.
register match.)
Either one pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi
pin.
Forced Cutoff .)
n+1
m +1
m -n
Specification
(Active level is low)
20. Timer RD