R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 525

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 488 of 802
Figure 23.3
• Transmit Timing Example (Internal Clock Selected)
• Receive Timing Example (External Clock Selected)
SiTIC register
UiC1 register
UiC0 register
UiC1 register
SiRIC register
Transfer clock
UiC1 register
TXEPT bit in
UiC1 register
UiC1 register
UiC1 register
RE bit in
TE bit in
TE bit in
IR bit in
The above applies under the following conditions:
RI bit in
TI bit in
TI bit in
IR bit in
The above applies under the following conditions:
The following should be met when a high-level is applied to the CLKi pin before receiving data:
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0
• UiIRS bit in UiC1 register = 0
TXDi
fEXT: Frequency of external clock
i = 0 or 1
CLKi
CLKi
RXDi
(transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
(interrupt request generation when the transmit buffer is empty)
• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0
• TE bit in UiC1 register = 1 (transmission enabled)
• RE bit in UiC1 register = 1 (reception enabled)
• Dummy data write to the UiTB register
(transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data set in UiTB register
Dummy data set in UiTB register
Data transfer from UARTi receive register
Data transfer from UiTB register to UARTi transmit register
Data transfer from UiTB register to UARTi transmit register
D0
D0
D1
D1
D2 D3
D2 D3
TCLK
Oct 30, 2009
1/fEXT
to UiRB register
D4 D5
D4 D5
TC
Received data capture
D6 D7
D6
Set to 0 when an interrupt request is acknowledged or by a program.
D7
D0 D1
D0 D1
Set to 0 when an interrupt request is acknowledged or by a program.
D2 D3
D2
Data read from UiRB register
D3
D4 D5
D4 D5
D6
TC = TCLK = 2(n+1)/fi
D7
fi: Frequency of UiBRG count source (f1, f8, f32, fC)
n: Value set in UiBRG register
Pulsing stops because TE bit is set to 0.
23. Serial Interface (UARTi (i = 0 or 1))
D0 D1
D2 D3
D4 D5
D6
D7