R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 634

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 597 of 802
27.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figures 27.7 and 27.8 show the Operating Timing in Master Receive Mode (I
The receive procedure and operation in master receive mode are as follows:
(1) After setting the TEND bit in the ICSR register to 0, set the TRS bit in the ICCR1 register to 0 to switch
(2) Dummy reading the ICDRR register starts receive operation. The receive clock is output in synchronization
(3) When one frame of data reception is completed, the RDRF bit in the ICSR register is set to 1 at the rising
(4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set to 1.
(5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (next receive
(6) When the RDRF bit is set to 1 at the rising edge of the 9th clock cycle of the receive clock, generate a stop
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0 (next
(8) Return to slave receive mode.
from master transmit mode to master receive mode. Then set the TDRE bit in the ICSR register to 0.
with the internal clock and data is received. The master device outputs the level set by the ACKBT bit in
the ICIER register to the SDA pin at the rising edge of the 9th clock cycle of the receive clock.
edge of the 9th clock cycle of the receive clock. If the ICDRR register is read at this time, the received data
can be read and the RDRF bit is set to 0 simultaneously.
If reading the ICDRR register is delayed by another process and the 8th clock cycle falls while the RDRF
bit is set to 1, the SCL signal is fixed low until the ICDRR register is read.
operation disabled) before reading the ICDRR register, stop condition generation is enabled after the next
receive operation.
condition.
receive operation continues).
Master Receive Operation
Oct 30, 2009
2
C bus Interface Mode).
27. I
2
C bus Interface