R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 675

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 638 of 802
Figure 29.4
29.3.3
29.3.3.1
29.3.3.2
A software trigger, trigger from timer RD or timer RC, and external trigger are used as A/D conversion start
triggers.
Figure 29.4 shows the Block Diagram of A/D Conversion Start Control Unit.
A software trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (software
trigger).
The A/D conversion starts when the ADST bit in the ADCON0 register is set to 1 (A/D conversion starts).
This trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 01b (timer RD).
To use this function, make sure the following conditions are met:
•
•
•
•
When the IMFj bit in the TRDSRk register is changed from 0 to 1 under the above conditions, A/D conversion
starts.
Refer to 20. Timer RD, 20.4 Output Compare Function, 20.5 PWM Mode, 20.6 Reset Synchronous PWM
Mode, 20.7 Complementary PWM Mode, 20.8 PWM3 Mode for the details of timer RD and the output
compare function (timer mode, PWM mode, reset synchronous PWM mode, complementary PWM mode, and
PWM3 mode).
Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 01b (timer RD).
Timer RD is used in the output compare function (timer mode, PWM mode, reset synchronous PWM mode,
complementary PWM mode, and PWM3 mode).
The ADTRGjkE bit (j = A, B, C, D, k = 0 or 1) in the TRDADCR register is set to 1 (A/D trigger occurs at
compare match with TRDGRjk register).
The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts).
(TRDSRk register)
(TRCSR register)
A/D Conversion Start Conditions
ADTRG pin
j = A, B, C, D k = 0 or 1
ADCAP0, ADCAP1: Bits in ADMOD register
ADST: Bit in ADCON0 register
ADTRGjkE: Bit in TRDADCR register
ADTRGjE: Bit in TRCADCR register
INT7EN: Bit in INTEN1 register
IMFj: Bit in TRDSRk register
IMFj: Bit in TRCSR register
Software Trigger
Trigger from Timer RD
Block Diagram of A/D Conversion Start Control Unit
IMFj
IMFj
ADTRGjkE
ADTRGjE
Oct 30, 2009
INT7EN
ADST
= 00b
= 01b
= 10b
= 11b
ADCAP1 to ADCAP0
A/D conversion start trigger
29. A/D Converter