R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 427

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 390 of 802
20.7.6
Notes:
1. When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the
2. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
3. Set the ADCAP bit in the ADCON0 register to 1 (start by timer RD).
4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 013Ah
setting of the TRDPMR register.
stops).
is enabled.
Symbol
ADTRG
Symbol
STCLK
Bit
PWM3
CMD0
CMD1
ADEG
OLS0
OLS1
Timer RD Function Control Register (TRDFCR) in Complementary PWM
Mode
PWM3
b7
1
Combination mode select bit
Normal-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
Counter-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
A/D trigger enable bit
(in complementary PWM mode)
A/D trigger edge select bit
(in complementary PWM mode)
External clock input select bit
PWM3 mode select bit
STCLK
b6
0
Oct 30, 2009
Bit Name
ADEG
b5
0
(4)
ADTRG
(1, 2)
b4
0
OLS1
b1 b0
Other than above: Do not set.
0: Initial output at high, active level is low
1: Initial output at low, active level is high
0: Initial output at high, active level is low
1: Initial output at low, active level is high
0: A/D trigger disabled
1: A/D trigger enabled
0: A/D trigger is generated at compare match
1: A/D trigger is generated at underflow in the
0: External clock input disabled
1: External clock input enabled
Disabled in complementary PWM mode.
1 0: Complementary PWM mode
1 1: Complementary PWM mode
b3
0
between registers TRD0 and TRDGRA0
TRD1 register
(transfer from the buffer register to the
general register at TRD1 register underflow)
(transfer from the buffer register to the
general register at compare match with
registers TRD0 and TRDGRA0.)
OLS0
b2
0
CMD1
Function
b1
(3)
0
CMD0
b0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W