R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 300

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 263 of 802
19.2.5
Note:
Table 19.4
Notes:
Bit Symbol
1. The results of writing to these bits are as follows:
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
1. Edge selected by bits IOj0 and IOj1 (j = A, B, C, or D) in registers TRCIOR0 and TRCIOR1.
2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and TRCGRB).
IMFB
IMFC
IMFD
IMFA
OVF
Address 0123h
• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it. (The bit’s value remains 1 even
• The bit’s value remains unchanged if 1 is written to it.
Symbol
if it is set to 1 from 0 after being read as 0 and having 0 written to it.)
Symbol
Bit
IMFC
IMFD
IMFA
IMFB
OVF
Timer RC Status Register (TRCSR)
—
—
—
TRCIOA pin input edge
TRCIOB pin input edge
TRCIOC pin input edge
TRCIOD pin input edge
When the TRC register overflows.
Conditions for Setting Bit of Each Flag to 1
Input capture Function
OVF
b7
0
Input-capture/compare-match flag A
Input-capture/compare-match flag B
Input-capture/compare-match flag C
Input-capture/compare-match flag D
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Overflow flag
b6
—
1
Oct 30, 2009
Bit Name
Timer Mode
(1)
(1)
(1)
(1)
b5
—
1
When the values of registers TRC and TRCGRA match.
When the values of registers TRC and TRCGRB match.
When the values of registers TRC and TRCGRC match.
When the values of registers TRC and TRCGRD match.
Output Compare Function
b4
—
1
IMFD
[Condition for setting to 0]
Write 0 after reading.
[Condition for setting to 1]
Refer to Table 19.4 Conditions for Setting Bit
of Each Flag to 1 .
[Condition for setting to 0]
Write 0 after reading.
[Condition for setting to 1]
Refer to Table 19.4 Conditions for Setting Bit
of Each Flag to 1 .
b3
0
IMFC
b2
0
PWM Mode
Function
IMFB
(1)
(1)
b1
0
IMFA
b0
0
PWM2 Mode
(2)
(2)
19. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
—