R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 623

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 586 of 802
27.2.8
Notes:
1. Rewrite between transfer frames. When writing values other than 000b, write when the SCL signal is low.
2. When writing to bits BC0 to BC2, write 0 to the BCWP bit simultaneously using the MOV instruction.
3. After data including the acknowledge bit is transferred, these bits are automatically set to 000b. When a start
4. Do not rewrite when the clock synchronous serial format is used.
5. The setting value is valid in master mode with the I
6. Set to 0 when the I
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 019Ah
condition is detected, these bits are automatically set to 000b.
format or when the clock synchronous serial format is used.
Symbol
Symbol
BCWP
Bit
WAIT
MLS
BC0
BC1
BC2
IIC bus Mode Register (ICMR)
—
—
MLS
b7
0
Bit counter 2 to 0
BC write protect bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Reserved bit
Wait insertion bit
MSB first/LSB first select
bit
2
C bus format is used.
WAIT
Bit Name
b6
0
Oct 30, 2009
(5)
b5
—
0
I
(Read: Number of remaining transfer bits;
b2 b1 b0
Clock synchronous serial format
(Read: Number of remaining transfer bits;
b2 b1 b0
When rewriting bits BC0 to BC2, write 0 simultaneously.
When read, the content is 1.
Set to 0.
0: No wait states
1: Wait state
0: Data transfer with MSB first
1: Data transfer with LSB first
2
Write: Number of next transfer data bits).
0 0 0: 9 bits
0 0 1: 2 bits
0 1 0: 3 bits
0 1 1: 4 bits
1 0 0: 5 bits
1 0 1: 6 bits
1 1 0: 7 bits
1 1 1: 8 bits
Write: Always 000b).
0 0 0: 8 bits
0 0 1: 1 bit
0 1 0: 2 bits
0 1 1: 3 bits
1 0 0: 4 bits
1 0 1: 5 bits
1 1 0: 6 bits
1 1 1: 7 bits
C bus format
(Data and the acknowledge bit are transferred successively)
(After the clock of the last data bit falls, a low-level period is
extended for two transfer clocks)
b4
—
1
2
(3)
BCWP
C bus format. It is invalid in slave mode with the I
b3
1
BC2
b2
0
Function
(6)
BC1
b1
0
(1, 2)
BC0
b0
0
27. I
(2, 4)
2
C bus Interface
2
C bus
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—